1. Field of the Invention
This invention relates to a method of fabricating a thin film transistor, and more particularly to a method of fabricating a thin film transistor of stagger structure.
2. Description of the Related Art
A thin film transistor using a thin film such as an amorphous silicon thin film, etc. as a semiconductor layer has attracted attention recently. For example, a plurality of transistors is integrated two dimensionally on a large, inexpensive substrate, such as glass, so as to form an active matrix which is combined with liquid crystal so as to form a panel display.
A stagger structure is given as a typical example of an embodiment of the structure of a conventional thin film transistor. FIG. 2 shows a stagger structure in which a gate electrode is provided at the side opposite to source and drain electrodes with respect to a semiconductive active layer.
For instance, a thin film transistor of the stagger structure is fabricated by successively forming on a glass substrate 101 an electrode 102, a gate insulating layer 103, an amorphous silicon i layer as an active semiconductor layer 104 an amorphous silicon n.sup.+ layer 105 as an ohmic contact (formation) layer, a source electrode 106 and a drain electrode 107.
In this configuration, however, the following problem are likely to occur. When the inner ends of the source and drain electrodes terminate outside of the ends of the gate electrode, an unchanneled portion is produced, whereby the transistor is held off. When the inner ends of the source and drain electrodes extend inside the end of the gate electrode, the source and drain electrodes, overlap the gate electrode thereby increasing connection capacity and lowering response speed.
Accordingly, it is to be desired that the inner ends of the source and drain electrodes be aligned with the end of the gate electrode in executing the patterning of the source electrode and the drain electrode. Thus, mask alignment requires high accuracy.
To obviate the aforementioned problem, the inventor of this invention proposed the following configuration for the purpose of providing a thin film transistor in which high accuracy mask alignment is not required and incidental capacity caused by the overlapping between the gate electrode and the source and drain electrodes is decreased so as to increase responsive speed. This is disclosed in my Japanese patent application No. 261518/1984, which was published on June 26, 1986 as Japanese Laid-open patent application No. 61-139069.
FIG. 3 shows such a thin-film transistor in which an amorphous silicon n.sup.+ layer (ohmic contact forming layer) corresponding to the source and drain areas is defined by an upper insulating layer interposed therebetween and it is configurated such that the inner ends of the source and drain areas are aligned with the ends of the gate electrode.
FIGS. 4(a) through 4(f) show an example of the process for forming the thin film transistor of FIG. 3 as disclosed in my Japanese Laid-open patent application No. 61-139069. In FIG. 4(a), a gate electrode 202 made of a chrome layer is patterned on a transparent glass substrate 201, and thereafter a silicon dioxide layer or silicon nitride layer is formed as a gate insulating layer 203.
Thereafter, amorphous silicon i layer 204 is formed as a semiconductor active layer as shown in FIG. 4(b).
Then, after the silicon dioxide layer or silicon nitride layer 206 is deposited, light is exposed from the substrate side under the state in which posi-resist 209 is coated as shown in FIG. 4(c), so that an image G of the gate electrode 202 is formed in the posi-resist 209.
Subsequently, after the development of the posi-resist 209 and the etching of the silicon dioxide layer or silicon nitride layer, the posi-resist pattern 209 and the upper insulating layer 206 are formed as shown in FIG. 4(d).
Furthermore, as shown in FIG. 4(e), an amorphous silicon n.sup.+ layer 205 is formed as an ohmic contact formation layer, and a thin chrome layer 208' is formed as a layer for forming the source and drain electrodes.
Thereafter, the amorphous silicon n.sup.+ layer 205 and the thin chrome layer 208' on the upper insulating layer 206, that is, the gate electrode 202, are removed by means of a lift off method, so that the ohmic contact formation layer 205 and source and drain electrodes 207 and 208 are patterned so as to form aluminum layer 210' as the wiring of the source and drain electrodes as shown in FIG. 4(f).
And finally, patterning is executed by means of the photo-lithography method so as to remove the outer edges of the ohmic contact layer and semiconductor active layer (FIG. 3).
The reason why the source and drain electrodes 207 and 208, and the electrode interconnection layer 210 are formed in the separate processes are as follows. In the patterning process by means of the lift-off method, patterning can be carried out only for a film sufficiently thinner than the resist pattern. In order to lift off the chrome layer and the amorphous silicon n.sup.+ layer concurrently, the chrome layer must be thin. As the source and drain electrode, a considerably thin layer may be used. However, when the interconnection layer is long, as resistance increases, considerable thickness is needed. Thus, the method above-described is usually adopted.
However, in this method, the formation of the source and drain electrodes (and the interconnection layer) requires a double use of metal film formation processes. Therefore, the steps are increased, and working efficiency is decreased.